Digital design experience with opensource hardware description languages (Chisel/SpinalHDL)

Here you find the details for the internship named "Digital design experience with opensource hardware description languages (Chisel/SpinalHDL)" in the company Nokia.

Name: Digital design experience with opensource hardware description languages (Chisel/SpinalHDL)
Company: Nokia

The team you’ll be part of
The pandemic has highlighted how important telecoms networks are to society. Nokia’s Network Infrastructure group is at the heart of a revolution to bring more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise.

The Fixed Networks Division is one of the key divisions in Nokia focusing on making Ultra Broadband Access possible for all users in the world. The fixed access product portfolio consists out of Fiber and Copper Access technology. In both domains the ASIC and FPGA System On Chips (SoC’s) are the heart of the system, making it possible for Nokia to have differentiating products at the right cost points.

Continuous innovation is required in the Fiber To The Home (FTTH) product line with next generation PON technologies.
The System On Chip (SoC) development team of Nokia Fixed Networks is based in Antwerp and the team is working
on the next generation chipset that will be delivering the product innovations of the coming years.

This team is offering students the possibility for an internship project (6 weeks) in the summer 2023.

What you will learn and contribute to:
- you can get a 6 weeks experience in a state-of-the-art SoC development team.
- your focus will be on the digital design of a specific block/module IP using open source hardware description langues like Chisel and SpinalHDL
- you will work to understand the requirements of the target module IP for which there is already an implementation available in (system)verilog
- you will make an implementation of the digital design using Chisel and SpinalHDL and compare the results
- you will validate the design with a unit level verification to ensure compatibility with the existing implementation (Using RTL simulator)
- you will go through synthesis of the design and check area, power and timing closure of the design if time allows

Target profiles:
    In industries:
      Required special knowledge:

      Duration: 3 months
      Paid: Nee
      Net wage: -
      Foreign: Nee
      Contact: Nadia Beutels (University Relations and Talent Attraction Specialist)