Power Reduction Techniques for 6G Hardware

Here you find the details for the internship named "Power Reduction Techniques for 6G Hardware" in the company Nokia.

Name: Power Reduction Techniques for 6G Hardware
Company: Nokia

The team you'll be part of

Nokia Bell Labs is the world-renowned research arm of Nokia, having invented many of the foundational technologies that underpin information and communications networks and all digital devices and systems. This research has produced nine Nobel Prizes, five Turing Awards and numerous other awards.

What you will learn and contribute to

Digital Signal Processors (DSP) are typically used to implement baseband signal processing algorithms in the physical layer of wireless communication systems. DSPs help to achieve low power consumption while meeting the high computational power demands of the baseband signal processing algorithms. However, achieving low power consumption will be a difficult challenge in 6G communication systems. This is mainly because of the massive throughput increase in 6G wireless systems using higher spectrum bands using Massive MIMO (Multiple Input Multiple Output) and beamforming with a large number of antenna elements. When the DSPs for 6G baseband processing are implemented with traditional approaches, the processing power and power density of such systems would grow exponentially due to the drastic increase in data-rate that needs to be processed by the compute-intensive signal processing algorithms.

Since the power consumed by the DSP processors is mainly due to the high activity in the compute logic, memory and the interconnect, novel techniques are required to reduce switching activity and thereby the active power consumption. Different activity reduction techniques can be applied at algorithmic-level, architecture-level or at gate-level, however, this needs to be done carefully by analyzing the scenarios under which the system is operating to minimize the overall performance impact.

The goal of this internship is to devise novel activity reduction techniques to reduce active power dissipation and analyze the impact on throughput performance on system level in a 6G physical layer architecture.

Key responsibilities:

- Literature study of physical layer hardware architecture and different active power reduction techniques.
- Develop a framework that allows simulation and evaluation of wireless baseband signal processing performance
- Propose suitable active power reduction techniques based on the analysis of activity patterns in the different signal processing functions.
- Devise the proposed architectural solutions and perform simulation and evaluate the impact on performance.
- Validate and compare the proposed solutions in terms of area usage and power consumption.

Target profiles:
    In industries:
      Required special knowledge:

      Duration: 3 months
      Paid: Nee
      Net wage: -
      Foreign: Nee
      Contact: Nadia Beutels (University Relations and Talent Attraction Specialist)