The Analog Layout Engineer will be joining our team to develop the next generation of CMOS image sensors. In a rapidly developing industry, we are looking for talent to help drive our innovation and continuous improvements to be technology leaders in the industry. You will do chip and block level layout, as well as chip level integration, as well as performing all necessary physical verification of our state of the art image sensors. You will be mentored by industry experts and will be able to grow your knowledge and experience.

Duties & Responsibilities:
• Carry out block level and chip level full custom analog layout, and chip level integration to ensure timely completion of an ASIC.
• Work with design engineers on chip architectural designs, floor planning and pad frame decisions.
• Physical verification using Calibre.
• Script layout operations with Cadence Skill.
• Contribute to continuous improvement of the design methodology.

• Minimum MSEE in electrical engineering. Prior analog layout experience is a plus.
• Excellent command of English as a working language.
• Good understanding of CMOS fabrication processes.
• Knowledge of analog layout techniques.
• Knowledge of Cadence Virtuoso.
• Knowledge of Siemens EDA Calibre DRC/LVS.
• Knowledge of scripting languages like Python is a plus.
• Knowledge of Cadence Skill is a plus.